The present invention relates to a counter, and more particularly to an asynchronous counter having programmable input for selecting a predetermined number of events to be counted.
In horizontal deflection systems of display devices such as oscilloscopes and logic analyzers, a sweep-gating circuit generates signals which control the initiation and transit of a waveform representation being displayed. The control signals generated by the sweep-gating circuit comprise an unblanking signal and a sweep-gating signal. The sweep-gating circuit is enabled or switched from a first stable state to a second stable state in response to a trigger signal developed from a selectable source such as an internal trigger pickoff circuit or a source external to the display device. A time-base generator circuit is responsive to the sweep-gating signal to generate a ramp output voltage or sweep signal which controls the horizontal presentation of the signal being displayed. In a cathode-ray tube (CRT) oscilloscope, a horizontal amplifier receiving the ramped sweep signal applies a push-pull analog of the ramp signal to horizontal-deflection elements of the CRT, thereby moving the electron beam steadily across the screen of the CRT.
Delayed trigger signals are generated and utilized in display devices, e.g., to display a portion of a waveform or a single selected pulse from a "bit stream" or train of pulses that follows a starting event or reference signal. Such delayed trigger signals were commonly developed with analog circuits; however, with the advent of complex digital equipment having extremely long pulse trains, signal jitter became a considerable problem. If signal jitter is excessive it can exceed the time between two adjacent pulses of a bit stream being displayed, and the particular pulse or the area of interest which needs to be displayed may be displayed intermittently or not at all. To overcome this problem, display devices utilize a digital counter circuit to develop the delayed trigger signal. Conventionally the counter is of the kind which can be preset, e.g., manually, to a desired number. The counter is reset at the end of each sweep of the display. At the beginning of each sweep of the primary time-base system, the counter starts counting the number of delayed time-base trigger pulses. When the counter reaches the preset number, the delayed time-base sweep is triggered. Pulses to be displayed are thus identified by their numbered position in the train of pulses and not by the time at which they occur with respect to the starting point. It is in such preset or programmable counters where my invention finds application.
Conventional implementations of programmable counters generally utilize synchronous coupling between stages of the counter. Successive stages of synchronous counters require increasingly complex gating structures to generate logic states for input to the next succeeding state of the counter even when JK flip-flops or bistables are used to advantage. Synchronus circuits require that the various logical operations be synchronized with respect to some reference time by a sequence of reference signals or clock pulses; clock pulses must be supplied to each and every switching circuit within a synchronous logic array which is a considerable disadvantage in itself, particularly when the circuits are implemented as microelectronic elements (integrated circuits).
In view of the foregoing, it is an object of my invention to provide an improved programmable counter having asynchronous coupling between stages of the counter.
It is a further object of my invention to provide an improved programmable ripple counter utilizing exclusive OR gates.